1. Field of the Invention
The present invention is directed generally to the field of testing semiconductor devices and, more particularly, to the generation of clock signals for controlling the testing operation of such devices. The present invention is particularly aimed at the problem of applying electrical signals to and measuring the response from semiconductor devices at precise and accurate time intervals.
2. Background Art
Many high-speed semiconductor devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc. rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. Additionally, new types of circuit architectures such as RAMBUS and DDR SDRAM require individual parts to work in unison even though such parts may individually operate at different speeds.
As a result, the ability to control the operation of a part through the generation of local clock signals has become increasingly more important. Moreover, such delay generators may be used in data path instead of clock path to control timing on per-bit basis that requires even greater accuracy.
A problem arises because it is often desired to delay signals at time intervals shorter than one period of the master oscillator. For example, the master oscillator might have a frequency of 100 MHz. Such an oscillator has a period of 10 nsec. However, in the tester it may be desired to place timing edges with precision of 5 psec and an accuracy of 25 psec.
This is typically implemented by using a delay line to form a timing vernier as is shown in the prior art. The signal passes through the delay line which has taps spaced closely apart in time. By selecting the appropriate taps several signals with intermediate timing can be generated. This procedure has been discussed in some detail in U.S. Pat. No. 4,511,846 and U.S. Pat. No. 4,837,521.
The early prior art is primarily concerned with circuits having constant current flowing through the logic elements and not much sensible to environmental parameters. However, as integrated circuit technology has progressed and demanded higher speed, more accurate and more complicated testing equipment, a problem arises to be applied to the timing vernier circuitry is that logic propagation delays are dependent upon the power supply voltage and the temperature of the silicon substrate.
As for the supply voltage sensitivity, it can be managed by very tightly regulating the supply voltage, though this adds cost to the test system, while the temperature of the substrate is much more difficult to control.
If the power dissipation of a circuit is constant, the substrate temperature can be controlled by placing the circuit in a temperature controlled oven as has been known in the prior art for many years. However, when the power dissipation is a result of capacitive charging and discharging, it is approximately proportional to the square of the operating frequency. This means that if the circuit operating frequency were to suddenly increase, as it will in many common test modes, the power dissipation may easily increase by a factor of 100. This sudden burst of power is very difficult to account for with an oven.
Additionally, the problem of variable environmental parameters can be solved as suggested in U.S. Pat. No. 6,092,030, when the effect of the significant environmental variables is measured and an adjustment made to the delay circuitry to compensate for the changes in the environmental variable is stored in a memory. Circuitry is designed into the integrated circuit that will measure the appropriate environmental variable or variables. The results of the measurement are used to adjust the delay so that the timing edges are in the correct location with respect to the master oscillator.
However, the above technical solution requires continuos monitoring and updating compensation values and also frequent re-calibration of adjustment coefficients to provide accurate timing which is a costly and time consuming operation affecting timing accuracy.
It is therefore an object of the present invention to provide a system and method for supplying accurate and constant time delays which do not depend on such environment parameters as temperature variations and do not require continuous update, but allows for simple and cost-effective maintenance.